DESIGN OF A DELAY-LOCKED LOOP WITH A DAC-CONTROLLED ANALOG DELAY LINE A Thesis Presented in Partial Fulfillment of the Requirements for the Degree of Master of Science with a Major in Electrical Engineering

Analog Delay Line, " has been reviewed in final form. Permission, as indicated by the signatures and dates given below, is now granted to submit final copies to the College of Graduate Studies for approval. ABSTRACT High-speed synchronous interface circuits require that the controlling clock signals be accurately aligned. A dynamic de-skew circuit can be used to ensure good clock alignment across variations in process, voltage, and temperature variations (PVT). The delay-locked loop (DLL) is such a circuit, using a first-order closed-loop architecture that dynamically aligns its output clock signal with a reference clock signal. Two basic types of DLL architectures are currently used: analog and digital. The analog DLL uses a continuously variable delay line to remove the skew between the output clock and the reference clock. A digital delay line uses digital elements, making the design more simple and portable, but with quantized steps in the delay time. Typical DLL architectures are explained, as well as the factors that introduce error in the accuracy of synchronized output. The design of a DLL that uses a differential, analog delay line is presented. A segmented, current-steering digital-to-analog converter (DAC) is designed. This DAC controls the delay line in increments of the DAC resolution. A synchronous up/down counter is used to control the DAC inputs. An arbiter is developed for phase detection. The DLL initialization control circuitry is explained, and final performance characteristics across PVT corners are presented.